1. Field of the Invention
The present invention relates to a synchronization device in a receiving device operated in a spread spectrum communications system.
2. Description of the Related Art
Recently, wireless communications such as portable telephone, etc. are widely used, and therefore it is important to effectively use the frequency channels so that a large number of subscribers can use their portable telephones. To solve this problem, a frequency division multiplexing system limits a band to be assigned to one frequency channel to accommodate the largest possible number of frequency channels in one frequency band.
It is also effective to limit the time of occupying one frequency channel by one subscriber to assign a channel to each subscriber after dividing communications time. It is a time division multiplexing system.
Another effective system is a spread spectrum system. For example, it is realized by superimposing a predetermined signal having a frequency band much larger than a base band signal on a phase-shift-keying modulated base band signal to spread the frequency band of a signal and send it as an electric wave.
This spread spectrum communications system can be a direct sequence (DS) system, a frequency hopping system, a time hopping system, etc. depending on the spreading method. Described below is the DS system.
In the DS system, a pseudo noise (PN) code is used as a predetermined signal to spread the frequency band. The PN code refers to binary data transmitted much faster than normal transmission data. The frequency band of the transmission data spread by the PN code is much broader than that of the original transmission data.
In the receiving equipment, a reverse-spreading process is performed by multiplying the data signal spread-spectrum-modulated in the transmitting equipment by the PN code used by the transmitting equipment so that the original transmission data can be retrieved. At this time, the phase of the PN code by which the received data is multiplied should be the same as that of the PN code used by the transmitting equipment. Therefore, a synchronizing process is performed for phasing.
FIG. 1 shows the configuration of a part of the conventional spread spectrum communications system.
A multiplier 111 multiplies the data transferred on the carrier from the transmitting equipment by an output signal from a crystal oscillator 112. The frequency of the carrier can be, for example, 2.4GHz. The crystal oscillator 112 outputs a periodic wave having the same frequency as the above described periodic wave, that is, 2.4GHz. A low-pass filter 113 passes only a signal around the base band, and filters the output signal from the multiplier 111. A limiter 114 monitors the output value from the low-pass filter 113 in one-chip units of PN codes, and binarizes (represents by digits) through the collation between the output value and a predetermined limit value. That is, the limiter 114 performs the 1-bit A/D converting process.
A PN code generation circuit 117 provides a correlation unit 118 with a PN code having the same pattern as the PN code multiplied in the transmitting device. The correlation unit 118 has a matched filter, and detects the phase-synchronization of a PN code in the transmitting and receiving devices at the timing of a peak value (detection of correlation) of the output when the output signals from the multiplier 111 are sequentially input. Then, it outputs data being regenerated by multiplying the signal output from the multiplier 111 at the timing by the PN code as reproduced data.
In the spread spectrum communications system, a reverse-spreading process should be performed by multiplying a PN code in the receiving device in synchronism with the PN code multiplied in the transmitting device.
FIGS. 2A through 2C show examples showing the conventional configuration for maintaining synchronization.
In the configuration shown in FIG. 2A, a maximum value detector 122 monitors the correlation value output from a correlation unit 121, and stores the timing at which the maximum value of the correlation value is detected. The information about the timing at which the maximum value has been detected is transmitted to a synchronous point comparator 123, and it is determined whether or not the timing (synchronous point) at which the maximum correlation value is obtained is shifting. When the synchronous point shifts, it indicates that the timing of the sampling clock used in the transmitting device is asynchronous with the timing of the sampling clock used in the receiving device. Therefore, the timing should be amended to correctly receive data in the receiving equipment. Using the synchronous point comparison information (a signal indicating how the timings of the maximum correlation values deviate from each other), the voltage, etc. applied to an oscillator 124 is controlled to adjust the output timing or the phase of a sampling clock. Thus, the timing at which the maximum correlation value is obtained is not deviated to stably receive the data.
With the configuration shown in FIG. 2B, the correlation unit 121 outputs a correlation value. The maximum value detector 122 detects a timing at which the maximum value detector 122 detects the maximum correlation value. The synchronous point comparator 123 outputs a control signal to control the oscillator 124 according to the synchronous point comparison information indicating whether or not the timing has deviated. A PN code generator 125 outputs a PN code to the correlation unit 121 based on the signal of a frequency oscillated by the oscillator 124, adjusts the timing (position of a synchronous point) at which the maximum correlation value can be obtained, and thus performs a control process to stabilize the position of a synchronous point. Since the PN-code multiplication can be performed in synchronism with the signal transmitted from the transmitting equipment, a correct signal can be received.
With the configuration shown in FIG. 2C, as in the above described configuration, the correlation unit 121 outputs a correlation value. The maximum value detector 122 detects the position of a synchronous point at which the maximum correlation value can be obtained. The synchronous point comparator 123 detects the deviation of the position of a synchronous point. With the configuration shown in FIG. 2C, the output from an oscillator 127 is not used as is in the correlation unit 121, but is input to a divider 126, and then input to the correlation unit 121 after controlling the phase of the sampling clock.
Thus, in the spread spectrum communications system, a correct signal should be received with synchronism by generating a sampling clock in the receiving equipment in a way that the sampling clock agrees in phase and synchronism with the sampling clock at which the transmitting equipment performs a PN-code multiplication.
FIG. 3 shows an example of the configuration of the digital matched filter which is a correlation unit. In this example, 128 chips are assigned to 1-bit transfer data, and a double-oversampling system is used to enhance the precision in detecting correlation.
Flipflops 131-1 through 131-128 can be, for example, a flipflop group for storing PN codes generated by the PN code generation circuit 125. The Q output of the flipflop 131-i is applied to the D terminal of the flipflop 131-i+1. The PN code applied to the D terminal of the flipflop 131-1 is sequentially shifted step by step using the sampling clock. The clock stops when a 128-chip PN code is stored, and the value is stored.
Flipflops 132-1a, 132-1b, . . . , 132-128a, and 132-128b are a flipflop group for storing input data. The Q output of each flipflop is applied to the D terminal of the next flipflop. The input data applied to the D terminal of the flipflop 132-1a is shifted step by step by the sampling clock. The frequency of the sampling clock is double the frequency of the PN code (clock frequency of a chip) so that a double-oversampling process can be performed.
An adder 134 adds up the logical values output from the exclusive NOR circuits 133-1a, 133-1b, 133-128a, and 133-128b. That is, the number of exclusive NOR circuits which outputs 1 is obtained.
The sum1 computed by the adder 134 is input to a subtractor 135, a comparator 136, and a selector 137.
The subtractor 135 computes sum2=256-sum1 and outputs sum2 to comparator 136 and selector 137.
The comparator 136 compares sum1 with sum2. If sum1 &gt;sum2, then 1 is output. If sum1 .ltoreq.sum2, then 0 is output. The selector 137 outputs sum1 when the output value from the comparator 136 is 1, and outputs sum2 when the output value from the comparator 136 is 0.
In the receiving equipment, there is a data clock for generating a timing at which output data can be obtained in addition to the sampling clock for use in multiplying a reception signal by the PN code. The output data is formed in a way that one bit is output on one cycle of data clock. This bit outputs data corresponding to the largest correlation value in all values obtained in the correlation unit on one cycle of the data clock. However, a correlation value can be variable for each timing of a sampling clock, and data can be generated corresponding to the maximum correlation value on one cycle of the data clock even without synchronization. Therefore, wrong data may be inserted or correct data may be lost unless only one correlation value indicating the correct synchronization appears on one cycle (window) of the data clock.
FIGS. 4A through 4C show the problems with the case where clocks are not in synchronism with each other between the transmission equipment and the receiving equipment.
In each of FIGS. 4A through 4C, the correlation value is indicated on top among the three values at each timing. Each of the peaks indicates a synchronous point. Indicated below each correlation value is a data clock, and one cycle of the data clock is hereinafter referred to as a window. Indicated at the bottom among the three values is a counter value in synchronism with the sampling clock.
As shown in FIG. 4A, data can be correctly regenerated when one synchronous point exists in one window. That is, a data value corresponding to the maximum correlation value detected by the maximum value detector is stored in one window. At the right end of the window (at the end of one cycle of the data clock), the data value corresponding to the stored maximum correlation value is output.
FIG. 4B shows the case where two synchronous points exist in one window. Since only one data value can be output in one window, one data value is regenerated although two data values should be regenerated corresponding to the two synchronous points in the above described window. As a result, one data value to be regenerated cannot be successfully output.
FIG. 4C also shows the case where no synchronous points exist in one window. In FIGS. 4A through 4C, the correlation values are similarly small at points other than the synchronous points. However, an actual correlation value can be any value at points other than a synchronous point. In FIGS. 4A through 4C, the correlation values indicate concave and convex figures (like ripples) between synchronous points. Therefore, if there are no synchronous points in one window in FIG. 4C, then a data value is regenerated at a timing corresponding to the largest correlation value in the correlation values forming ripples. However, since there are actually no synchronous points in this window, a wrong data value is regenerated.
If the clock indicates such a deviation, a synchronous point deviates in a window. If this occurs in series, the synchronous point deviates to the end of the window. When the synchronous point further deviates, it goes beyond the end of the window and enters the next window. In such a case, a problem of wrong data occurs (an excess piece of data is inserted or a piece of necessary data is lost).
Therefore, if a correct data value should be regenerated, one synchronous point is required to exist in one window. As described by referring to FIGS. 2A through C, an oscillator is operated to change the phase of the sampling clock to set one synchronous point in one window according to the conventional technology.
However, according to the conventional configuration, the clock must be controlled at a precision level equal to or higher than the PN code chip rate level or the sampling clock level, thereby requiring a difficult circuit configuration. Furthermore, a large-scale circuit is required and the entire system becomes costly.